IBM hails new 'block of flats' design breakthrough for ultra‑tiny chips

IBM has unveiled a new chip design that could cram roughly 100 billion transistors onto the surface of a fingernail – a size comparable to the most compact chips in use today.

Current industry standard nodes sit at about two nanometres (2 nm), roughly the width of a DNA double helix. IBM claims its NanoStack architecture can reach around 0.7 nm, which would make it the first chip to go below the one‑nanometre threshold.

According to IBM, a prototype using this technology performed 50 % faster than the company’s own 2 nm chips and used 70 % less power. The company showed similar performance gains when first introducing its 2 nm line in 2021.

The design stacks layers of transistors vertically – a 3‑D approach – which the firm likened to a 'block of flats' rather than a single‑story building. Prof. Alan Woodward of Surrey University called the ambition 'comparable to a 100‑story skyscraper'.

The key challenge for 3‑D chips is heat dissipation – as layers stack, heat can rise and damage components. Also, ultra‑thin insulation layers can prevent transistors from fully turning off, crippling performance.

Lead IBM Research director Jay Gambetta said the approach 're‑invent[s] the way chips are built, providing dramatically more power and energy efficiency'.

While the technology is promising, it will likely be years before the chips move to mass production, according to IBM experts.